HEADER {
	INLIB  = ../source/Johnson_count.gds
	OUTLIB = ../results/TOPCELLNAME_err
	OUTLIB_PATH = ../results/    /* For Synopsys internal use only! */
	BLOCK = Johnson_count
	FORMAT = GDSII
	OUTPUT_FORMAT = LTL
	OUTPUT_LAYOUT_PATH = /remote/SCRATCH_fs01/ANI_AL/Ani/fullflow/hercules/lvs/results
	COMPARE_DIR = /remote/SCRATCH_fs01/ANI_AL/Ani/fullflow/hercules/lvs/results/TOPCELLNAME.run_details/compare
	RUN_DETAILS_DIR = /remote/SCRATCH_fs01/ANI_AL/Ani/fullflow/hercules/lvs/results/TOPCELLNAME.run_details
	SCHEMATIC = /remote/SCRATCH_fs01/ANI_AL/Ani/fullflow/hercules/lvs/source/Johnson_count.sp
	SCHEMATIC_FORMAT = SPICE
}
TECHNOLOGY_OPTIONS {
	EXPLODE_AREFS = FALSE
	EXPLODE_CELL_SIZE_PERCENT=70
	EXPLODE_CELL_SIZE_PERCENT_OF_TOP=70
	EXPLODE_BIG_SPARSE_CELL=TRUE
	POST_VCELL_EXPLODE_CELL_SIZE <= 10
	BAR_AUTO_EXPLODE=TRUE
	POST_VCELL_EXPLODE_LOW_MEMORY=TRUE
	VIA_AUTO_EXPLODE=TRUE
	SUBLEAF_AUTO_EXPLODE=6
	CELL_SIZE_AUTO_EXPLODE <= 10
	EXPLODE_DATA_CELL_LIMIT = 4
	POST_VCELL_EXPLODE_DATA_CELL_LIMIT = 12
	EXPLODE_HOLDING_CELL_LIMIT = 1
	EXPLODE_PLACEMENT_LIMIT = 1
	VCELL_PASS   {
		STYLE = PAIRS
		ITERATE_MAX = 15
		ARRAY_ID = TRUE
		EXPLODE_INTO_VCELL = FALSE
		MIN_COUNT = 20
		TOP_PERCENT_OF_VALUE = 40 
	}
}
OPTIONS {
	AUTO_SCHEMATIC_GLOBAL_ON=TRUE
	ERR_PREFIX = ERR
	GDSIN_OPTIONS= "-nl"
	IGNORE_CASE=TRUE
	LAYOUT_GROUND = { VSS VSS12 VSS25 }
	LAYOUT_POWER = { VDD VDD12 VDD25 }
	MAXIMUM_CELLNAME_LENGTH = 127
	MESSAGE_ERROR = { CMP-40 CMP-41 }
	NET_PREFIX = N_
	NETTRAN_OPTIONS= " -mprop "
	PRINT_ERRSUM_FILE=TRUE
	PROTOTYPE_PLACEMENTS = FALSE
	RESOLUTION=0.001
	SCHEMATIC_GROUND = { VSS VSS12 VSS25 }
	SCHEMATIC_POWER = { VDD VDD12 VDD25 }
	IUO_DEVICE_NAME_LIST = { n12, p12, n25, p25, n12_lvt, p12_lvt, n12_hvt, p12_hvt, rppoly, rnpoly, rppoly_wos, rnpoly_wos, rm1, rm2, rm3, rm4, rm5, rm6, rm7, rm8, rm9, ND, PD }
	IUO_SNAP_VALUES = [ 0.001 ]
}
EVACCESS_OPTIONS {
	PATH = /remote/SCRATCH_fs01/ANI_AL/Ani/fullflow/hercules/lvs/results/TOPCELLNAME.run_details/evaccess
	LIBRARY = Johnson_count
	CREATE_VIEWS = TRUE
}
TEXT_OPTIONS {
	USE_COLON_TEXT=TRUE
	TRUNCATE_FLAG=FALSE
	REMOVE_TEXT_FROM_SHORT=FALSE
	CONNECT_BY_NAME = MIXED_MODE
	ATTACH_TEXT = ALL
}
EXPLODE_OPTIONS {
	FLATTEN = { TOPCELLNAME }
}
ASSIGN { 
	NWELLi	(1)
	DNWi	(2)
	DIFFi	(3)
	DDMYi	(3;1)
	PIMPi	(4)
	NIMPi	(5)
	DIFF_25i	(6)
	PADi	(7)
	ESD_25	(8)
	SBLKi	(9)
	POi	(10)
	PODMYi	(10;1)
	M1i	(11)	text(11)
	M1DMYi	(11;1)
	M2i	(12)	text(12)
	M2DMYi	(12;1)
	M3i	(13)	text(13)
	M3DMYi	(13;1)
	M4i	(14)	text(14)
	M4DMYi	(14;1)
	M5i	(15)	text(15)
	M5DMYi	(15;1)
	M6i	(16)	text(16)
	M6DMYi	(16;1)
	M7i	(17)	text(17)
	M7DMYi	(17;1)
	M8i	(18)	text(18)
	M8DMYi	(18;1)
	M9i	(19)	text(19)
	M9DMYi	(19;1)
	COi	(20)
	VIA1i	(21)
	VIA2i	(22)
	VIA3i	(23)
	VIA4i	(24)
	VIA5i	(25)
	VIA6i	(26)
	VIA7i	(27)
	VIA8i	(28)
	HVTIMPi	(29)
	LVTIMPi	(30)
	M1PIN	(31)	text(31)
	M2PIN	(32)	text(32)
	M3PIN	(33)	text(33)
	M4PIN	(34)	text(34)
	M5PIN	(35)	text(35)
	M6PIN	(36)	text(36)
	M7PIN	(37)	text(37)
	M8PIN	(38)	text(38)
	M9PIN	(39)	text(39)
	HOTNWLi	(41)
	DIODi	(43)
	BJTDMYi	(44)
	RNWi	(45)
	RPOLYi	(46)
	RDIFFi	(47)
	LOGO	(48)
	IP	(49;49)	text(49;49)
	RM1i	(51)
	RM2i	(52)
	RM3i	(53)
	RM4i	(54)
	RM5i	(55)
	RM6i	(56)
	RM7i	(57)
	RM8i	(58)
	RM9i	(59)} HIERARCHY = ERR_1.HIERARCHY
CREATE_LAYER NWELLi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
		CHECK_INSTANCES = TRUE
	}
} TEMP=NWELLi
CREATE_LAYER DNWi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=DNWi
CREATE_LAYER DIFFi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=DIFFi
CREATE_LAYER DDMYi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=DDMYi
CREATE_LAYER PIMPi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=PIMPi
CREATE_LAYER NIMPi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=NIMPi
CREATE_LAYER DIFF_25i  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=DIFF_25i
CREATE_LAYER PADi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=PADi
CREATE_LAYER ESD_25  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=ESD_25
CREATE_LAYER SBLKi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=SBLKi
CREATE_LAYER POi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=POi
CREATE_LAYER PODMYi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=PODMYi
CREATE_LAYER M1i M1i.TEXT  {
	CREATE_TEXT = TRUE
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M1i TEXT=M1i.TEXT
CREATE_LAYER M1DMYi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M1DMYi
CREATE_LAYER M2i M2i.TEXT  {
	CREATE_TEXT = TRUE
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M2i TEXT=M2i.TEXT
CREATE_LAYER M2DMYi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M2DMYi
CREATE_LAYER M3i M3i.TEXT  {
	CREATE_TEXT = TRUE
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M3i TEXT=M3i.TEXT
CREATE_LAYER M3DMYi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M3DMYi
CREATE_LAYER M4i M4i.TEXT  {
	CREATE_TEXT = TRUE
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M4i TEXT=M4i.TEXT
CREATE_LAYER M4DMYi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M4DMYi
CREATE_LAYER M5i M5i.TEXT  {
	CREATE_TEXT = TRUE
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M5i TEXT=M5i.TEXT
CREATE_LAYER M5DMYi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M5DMYi
CREATE_LAYER M6i M6i.TEXT  {
	CREATE_TEXT = TRUE
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M6i TEXT=M6i.TEXT
CREATE_LAYER M6DMYi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M6DMYi
CREATE_LAYER M7i M7i.TEXT  {
	CREATE_TEXT = TRUE
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M7i TEXT=M7i.TEXT
CREATE_LAYER M7DMYi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M7DMYi
CREATE_LAYER M8i M8i.TEXT  {
	CREATE_TEXT = TRUE
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M8i TEXT=M8i.TEXT
CREATE_LAYER M8DMYi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M8DMYi
CREATE_LAYER M9i M9i.TEXT  {
	CREATE_TEXT = TRUE
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M9i TEXT=M9i.TEXT
CREATE_LAYER M9DMYi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M9DMYi
CREATE_LAYER COi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=COi
CREATE_LAYER VIA1i  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=VIA1i
CREATE_LAYER VIA2i  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=VIA2i
CREATE_LAYER VIA3i  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=VIA3i
CREATE_LAYER VIA4i  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=VIA4i
CREATE_LAYER VIA5i  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=VIA5i
CREATE_LAYER VIA6i  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=VIA6i
CREATE_LAYER VIA7i  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=VIA7i
CREATE_LAYER VIA8i  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=VIA8i
CREATE_LAYER HVTIMPi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=HVTIMPi
CREATE_LAYER LVTIMPi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=LVTIMPi
CREATE_LAYER M1PIN M1PIN.TEXT  {
	CREATE_TEXT = TRUE
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M1PIN TEXT=M1PIN.TEXT
CREATE_LAYER M2PIN M2PIN.TEXT  {
	CREATE_TEXT = TRUE
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M2PIN TEXT=M2PIN.TEXT
CREATE_LAYER M3PIN M3PIN.TEXT  {
	CREATE_TEXT = TRUE
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M3PIN TEXT=M3PIN.TEXT
CREATE_LAYER M4PIN M4PIN.TEXT  {
	CREATE_TEXT = TRUE
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M4PIN TEXT=M4PIN.TEXT
CREATE_LAYER M5PIN M5PIN.TEXT  {
	CREATE_TEXT = TRUE
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M5PIN TEXT=M5PIN.TEXT
CREATE_LAYER M6PIN M6PIN.TEXT  {
	CREATE_TEXT = TRUE
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M6PIN TEXT=M6PIN.TEXT
CREATE_LAYER M7PIN M7PIN.TEXT  {
	CREATE_TEXT = TRUE
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M7PIN TEXT=M7PIN.TEXT
CREATE_LAYER M8PIN M8PIN.TEXT  {
	CREATE_TEXT = TRUE
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M8PIN TEXT=M8PIN.TEXT
CREATE_LAYER M9PIN M9PIN.TEXT  {
	CREATE_TEXT = TRUE
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=M9PIN TEXT=M9PIN.TEXT
CREATE_LAYER HOTNWLi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=HOTNWLi
CREATE_LAYER DIODi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=DIODi
CREATE_LAYER BJTDMYi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=BJTDMYi
CREATE_LAYER RNWi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=RNWi
CREATE_LAYER RPOLYi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=RPOLYi
CREATE_LAYER RDIFFi  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=RDIFFi
CREATE_LAYER LOGO  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=LOGO
CREATE_LAYER IP IP.TEXT  {
	CREATE_TEXT = TRUE
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=IP TEXT=IP.TEXT
CREATE_LAYER RM1i  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=RM1i
CREATE_LAYER RM2i  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=RM2i
CREATE_LAYER RM3i  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=RM3i
CREATE_LAYER RM4i  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=RM4i
CREATE_LAYER RM5i  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=RM5i
CREATE_LAYER RM6i  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=RM6i
CREATE_LAYER RM7i  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=RM7i
CREATE_LAYER RM8i  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=RM8i
CREATE_LAYER RM9i  {
	SEQUENCE = SNAP_GRID
	SNAP_OPTIONS = {
		SNAP = 0.001
		VERBOSE = TRUE
	}
	GRID_OPTIONS = {
		GRID = 0.005
		CHECK_45 = TRUE
	}
} TEMP=RM9i
HIERARCHY_CLEANUP HIERARCHY = ERR_2.HIERARCHY
CLEAN_PREPROCESSOR
COPY NWELLi { } TEMP=nwell
COPY DIFFi { } TEMP=diff
COPY PIMPi { } TEMP=pimp
COPY NIMPi { } TEMP=nimp
COPY DIFF_25i { } TEMP=diff_25
COPY SBLKi { } TEMP=sblk
COPY POi { } TEMP=po
COPY M1i { } TEMP=m1
COPY M2i { } TEMP=m2
COPY M3i { } TEMP=m3
COPY M4i { } TEMP=m4
COPY M5i { } TEMP=m5
COPY M6i { } TEMP=m6
COPY M7i { } TEMP=m7
COPY M8i { } TEMP=m8
COPY M9i { } TEMP=m9
COPY COi { } TEMP=co
COPY VIA1i { } TEMP=via1
COPY VIA2i { } TEMP=via2
COPY VIA3i { } TEMP=via3
COPY VIA4i { } TEMP=via4
COPY VIA5i { } TEMP=via5
COPY VIA6i { } TEMP=via6
COPY VIA7i { } TEMP=via7
COPY VIA8i { } TEMP=via8
COPY HVTIMPi { } TEMP=hvtimp
COPY LVTIMPi { } TEMP=lvtimp
COPY RM1i { } TEMP=rm1
COPY RM2i { } TEMP=rm2
COPY RM3i { } TEMP=rm3
COPY RM4i { } TEMP=rm4
COPY RM5i { } TEMP=rm5
COPY RM6i { } TEMP=rm6
COPY RM7i { } TEMP=rm7
COPY RM8i { } TEMP=rm8
COPY RM9i { } TEMP=rm9
COPY DIODi { } TEMP=diod
COPY RNWi { } TEMP=rnw
COPY RPOLYi { } TEMP=rpoly
CELL_EXTENT {
	CELL_LIST = { * }
}TEMP=chip
SIZE chip { 
	OVERSIZE=1 } TEMP=bulk
BOOLEAN bulk NOT nwell { } TEMP=pwell
SELECT nwell INTERACT rnw {}TEMP=rnwel
SELECT nwell OUTSIDE rnwel {
	POINT_TOUCH=FALSE 
	LINE_TOUCH=FALSE }TEMP=nwnr
BOOLEAN nimp AND diff { } TEMP=ndiff
BOOLEAN pimp AND diff { } TEMP=pdiff
BOOLEAN ndiff AND pwell { } TEMP=nact
BOOLEAN pdiff AND nwnr { } TEMP=pact
BOOLEAN po NOT rpoly { } TEMP=ponr
BOOLEAN po AND rpoly { } TEMP=pores
BOOLEAN pores AND pimp { } TEMP=ppores
BOOLEAN pores AND nimp { } TEMP=npores
BOOLEAN ppores AND sblk { } TEMP=ppores_sblk
BOOLEAN npores AND sblk { } TEMP=npores_sblk
BOOLEAN po AND nact { } TEMP=ngate
BOOLEAN po AND pact { } TEMP=pgate
BOOLEAN ngate OR pgate { } TEMP=gate
SELECT hvtimp INTERACT lvtimp {
	COMMENT = "Interact of HVTIMP and LVTIMP is not allowed"}(163)
SELECT hvtimp INTERACT diff_25 {
	COMMENT = "Interact of HVTIMP and DIFF_25 is not allowed"}(163)
SELECT lvtimp INTERACT diff_25 {
	COMMENT = "Interact of LVTIMP and DIFF_25 is not allowed"}(163)
BOOLEAN ngate NOT (diff_25 OR hvtimp OR lvtimp) { } TEMP=ngate_12
BOOLEAN pgate NOT (diff_25 OR hvtimp OR lvtimp) { } TEMP=pgate_12
BOOLEAN ngate AND diff_25 { } TEMP=ngate_25
BOOLEAN pgate AND diff_25 { } TEMP=pgate_25
BOOLEAN ngate AND lvtimp { } TEMP=ngate_12_lvt
BOOLEAN pgate AND lvtimp { } TEMP=pgate_12_lvt
BOOLEAN ngate AND hvtimp { } TEMP=ngate_12_hvt
BOOLEAN pgate AND hvtimp { } TEMP=pgate_12_hvt
BOOLEAN pdiff AND pwell { } TEMP=ptap
BOOLEAN ndiff AND nwnr { } TEMP=ntap
BOOLEAN co AND diff { } TEMP=codiff
BOOLEAN co NOT diff { } TEMP=copoly
BOOLEAN nact NOT gate { } TEMP=nsd
BOOLEAN pact NOT gate { } TEMP=psd
BOOLEAN m1 AND rm1 { } TEMP=m1res
BOOLEAN m2 AND rm2 { } TEMP=m2res
BOOLEAN m3 AND rm3 { } TEMP=m3res
BOOLEAN m4 AND rm4 { } TEMP=m4res
BOOLEAN m5 AND rm5 { } TEMP=m5res
BOOLEAN m6 AND rm6 { } TEMP=m6res
BOOLEAN m7 AND rm7 { } TEMP=m7res
BOOLEAN m8 AND rm8 { } TEMP=m8res
BOOLEAN m9 AND rm9 { } TEMP=m9res
BOOLEAN m1 NOT rm1 { } TEMP=m1
BOOLEAN m2 NOT rm2 { } TEMP=m2
BOOLEAN m3 NOT rm3 { } TEMP=m3
BOOLEAN m4 NOT rm4 { } TEMP=m4
BOOLEAN m5 NOT rm5 { } TEMP=m5
BOOLEAN m6 NOT rm6 { } TEMP=m6
BOOLEAN m7 NOT rm7 { } TEMP=m7
BOOLEAN m8 NOT rm8 { } TEMP=m8
BOOLEAN m9 NOT rm9 { } TEMP=m9
SELECT diod INTERACT nact {
	POINT_TOUCH=FALSE 
	LINE_TOUCH=FALSE }TEMP=ndiffdio
SELECT diod INTERACT pact {
	POINT_TOUCH=FALSE 
	LINE_TOUCH=FALSE }TEMP=pdiffdio
COPY ptap { } TEMP=pwell_cont
COPY ntap { } TEMP=nwell_cont
PREPROCESS_DEVICE NMOS {
	ngate_12 {LAYERTYPE= DEVICE}TEMP=__PD_n12_ngate_12
	nsd {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_n12_nsd
	pwell {LAYERTYPE= TERM(3)}TEMP=__PD_n12_pwell
}
PREPROCESS_DEVICE PMOS {
	pgate_12 {LAYERTYPE= DEVICE}TEMP=__PD_p12_pgate_12
	psd {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_p12_psd
	nwnr {LAYERTYPE= TERM(3)}TEMP=__PD_p12_nwnr
}
PREPROCESS_DEVICE NMOS {
	ngate_25 {LAYERTYPE= DEVICE}TEMP=__PD_n25_ngate_25
	nsd {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_n25_nsd
	pwell {LAYERTYPE= TERM(3)}TEMP=__PD_n25_pwell
}
PREPROCESS_DEVICE PMOS {
	pgate_25 {LAYERTYPE= DEVICE}TEMP=__PD_p25_pgate_25
	psd {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_p25_psd
	nwnr {LAYERTYPE= TERM(3)}TEMP=__PD_p25_nwnr
}
PREPROCESS_DEVICE NMOS {
	ngate_12_lvt {LAYERTYPE= DEVICE}TEMP=__PD_n12_lvt_ngate_12_lvt
	nsd {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_n12_lvt_nsd
	pwell {LAYERTYPE= TERM(3)}TEMP=__PD_n12_lvt_pwell
}
PREPROCESS_DEVICE PMOS {
	pgate_12_lvt {LAYERTYPE= DEVICE}TEMP=__PD_p12_lvt_pgate_12_lvt
	psd {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_p12_lvt_psd
	nwnr {LAYERTYPE= TERM(3)}TEMP=__PD_p12_lvt_nwnr
}
PREPROCESS_DEVICE NMOS {
	ngate_12_hvt {LAYERTYPE= DEVICE}TEMP=__PD_n12_hvt_ngate_12_hvt
	nsd {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_n12_hvt_nsd
	pwell {LAYERTYPE= TERM(3)}TEMP=__PD_n12_hvt_pwell
}
PREPROCESS_DEVICE PMOS {
	pgate_12_hvt {LAYERTYPE= DEVICE}TEMP=__PD_p12_hvt_pgate_12_hvt
	psd {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_p12_hvt_psd
	nwnr {LAYERTYPE= TERM(3)}TEMP=__PD_p12_hvt_nwnr
}
PREPROCESS_DEVICE RES {
	ppores {LAYERTYPE= DEVICE}TEMP=__PD_rppoly_ppores
	ponr {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_rppoly_ponr
}
PREPROCESS_DEVICE RES {
	npores {LAYERTYPE= DEVICE}TEMP=__PD_rnpoly_npores
	ponr {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_rnpoly_ponr
}
PREPROCESS_DEVICE RES {
	ppores_sblk {LAYERTYPE= DEVICE}TEMP=__PD_rppoly_wos_ppores_sblk
	ponr {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_rppoly_wos_ponr
}
PREPROCESS_DEVICE RES {
	npores_sblk {LAYERTYPE= DEVICE}TEMP=__PD_rnpoly_wos_npores_sblk
	ponr {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_rnpoly_wos_ponr
}
PREPROCESS_DEVICE RES {
	m1res {LAYERTYPE= DEVICE}TEMP=__PD_rm1_m1res
	m1 {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_rm1_m1
}
PREPROCESS_DEVICE RES {
	m2res {LAYERTYPE= DEVICE}TEMP=__PD_rm2_m2res
	m2 {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_rm2_m2
}
PREPROCESS_DEVICE RES {
	m3res {LAYERTYPE= DEVICE}TEMP=__PD_rm3_m3res
	m3 {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_rm3_m3
}
PREPROCESS_DEVICE RES {
	m4res {LAYERTYPE= DEVICE}TEMP=__PD_rm4_m4res
	m4 {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_rm4_m4
}
PREPROCESS_DEVICE RES {
	m5res {LAYERTYPE= DEVICE}TEMP=__PD_rm5_m5res
	m5 {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_rm5_m5
}
PREPROCESS_DEVICE RES {
	m6res {LAYERTYPE= DEVICE}TEMP=__PD_rm6_m6res
	m6 {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_rm6_m6
}
PREPROCESS_DEVICE RES {
	m7res {LAYERTYPE= DEVICE}TEMP=__PD_rm7_m7res
	m7 {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_rm7_m7
}
PREPROCESS_DEVICE RES {
	m8res {LAYERTYPE= DEVICE}TEMP=__PD_rm8_m8res
	m8 {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_rm8_m8
}
PREPROCESS_DEVICE RES {
	m9res {LAYERTYPE= DEVICE}TEMP=__PD_rm9_m9res
	m9 {LAYERTYPE= TERM(1), TERM(2)}TEMP=__PD_rm9_m9
}
PREPROCESS_DEVICE DIODE {
	ndiffdio {LAYERTYPE= DEVICE}TEMP=__PD_ND_ndiffdio
	nsd {LAYERTYPE= TERM(1)}TEMP=__PD_ND_nsd
	pwell {LAYERTYPE= TERM(2)}TEMP=__PD_ND_pwell
}
PREPROCESS_DEVICE DIODE {
	pdiffdio {LAYERTYPE= DEVICE}TEMP=__PD_PD_pdiffdio
	psd {LAYERTYPE= TERM(1)}TEMP=__PD_PD_psd
	nwnr {LAYERTYPE= TERM(2)}TEMP=__PD_PD_nwnr
}
MERGE_DEVICE_LAYER {
	LAYERLIST = { ngate_12 __PD_n12_ngate_12 }
}TEMP=ngate_12
MERGE_DEVICE_LAYER {
	LAYERLIST = { nsd __PD_n12_nsd __PD_n25_nsd __PD_n12_lvt_nsd __PD_n12_hvt_nsd __PD_ND_nsd }
}TEMP=nsd
MERGE_DEVICE_LAYER {
	LAYERLIST = { pwell __PD_n12_pwell __PD_n25_pwell __PD_n12_lvt_pwell __PD_n12_hvt_pwell __PD_ND_pwell }
}TEMP=pwell
MERGE_DEVICE_LAYER {
	LAYERLIST = { pgate_12 __PD_p12_pgate_12 }
}TEMP=pgate_12
MERGE_DEVICE_LAYER {
	LAYERLIST = { psd __PD_p12_psd __PD_p25_psd __PD_p12_lvt_psd __PD_p12_hvt_psd __PD_PD_psd }
}TEMP=psd
MERGE_DEVICE_LAYER {
	LAYERLIST = { nwnr __PD_p12_nwnr __PD_p25_nwnr __PD_p12_lvt_nwnr __PD_p12_hvt_nwnr __PD_PD_nwnr }
}TEMP=nwnr
MERGE_DEVICE_LAYER {
	LAYERLIST = { ngate_25 __PD_n25_ngate_25 }
}TEMP=ngate_25
MERGE_DEVICE_LAYER {
	LAYERLIST = { pgate_25 __PD_p25_pgate_25 }
}TEMP=pgate_25
MERGE_DEVICE_LAYER {
	LAYERLIST = { ngate_12_lvt __PD_n12_lvt_ngate_12_lvt }
}TEMP=ngate_12_lvt
MERGE_DEVICE_LAYER {
	LAYERLIST = { pgate_12_lvt __PD_p12_lvt_pgate_12_lvt }
}TEMP=pgate_12_lvt
MERGE_DEVICE_LAYER {
	LAYERLIST = { ngate_12_hvt __PD_n12_hvt_ngate_12_hvt }
}TEMP=ngate_12_hvt
MERGE_DEVICE_LAYER {
	LAYERLIST = { pgate_12_hvt __PD_p12_hvt_pgate_12_hvt }
}TEMP=pgate_12_hvt
MERGE_DEVICE_LAYER {
	LAYERLIST = { ppores __PD_rppoly_ppores }
}TEMP=ppores
MERGE_DEVICE_LAYER {
	LAYERLIST = { ponr __PD_rppoly_ponr __PD_rnpoly_ponr __PD_rppoly_wos_ponr __PD_rnpoly_wos_ponr }
}TEMP=ponr
MERGE_DEVICE_LAYER {
	LAYERLIST = { npores __PD_rnpoly_npores }
}TEMP=npores
MERGE_DEVICE_LAYER {
	LAYERLIST = { ppores_sblk __PD_rppoly_wos_ppores_sblk }
}TEMP=ppores_sblk
MERGE_DEVICE_LAYER {
	LAYERLIST = { npores_sblk __PD_rnpoly_wos_npores_sblk }
}TEMP=npores_sblk
MERGE_DEVICE_LAYER {
	LAYERLIST = { m1res __PD_rm1_m1res }
}TEMP=m1res
MERGE_DEVICE_LAYER {
	LAYERLIST = { m1 __PD_rm1_m1 }
}TEMP=m1
MERGE_DEVICE_LAYER {
	LAYERLIST = { m2res __PD_rm2_m2res }
}TEMP=m2res
MERGE_DEVICE_LAYER {
	LAYERLIST = { m2 __PD_rm2_m2 }
}TEMP=m2
MERGE_DEVICE_LAYER {
	LAYERLIST = { m3res __PD_rm3_m3res }
}TEMP=m3res
MERGE_DEVICE_LAYER {
	LAYERLIST = { m3 __PD_rm3_m3 }
}TEMP=m3
MERGE_DEVICE_LAYER {
	LAYERLIST = { m4res __PD_rm4_m4res }
}TEMP=m4res
MERGE_DEVICE_LAYER {
	LAYERLIST = { m4 __PD_rm4_m4 }
}TEMP=m4
MERGE_DEVICE_LAYER {
	LAYERLIST = { m5res __PD_rm5_m5res }
}TEMP=m5res
MERGE_DEVICE_LAYER {
	LAYERLIST = { m5 __PD_rm5_m5 }
}TEMP=m5
MERGE_DEVICE_LAYER {
	LAYERLIST = { m6res __PD_rm6_m6res }
}TEMP=m6res
MERGE_DEVICE_LAYER {
	LAYERLIST = { m6 __PD_rm6_m6 }
}TEMP=m6
MERGE_DEVICE_LAYER {
	LAYERLIST = { m7res __PD_rm7_m7res }
}TEMP=m7res
MERGE_DEVICE_LAYER {
	LAYERLIST = { m7 __PD_rm7_m7 }
}TEMP=m7
MERGE_DEVICE_LAYER {
	LAYERLIST = { m8res __PD_rm8_m8res }
}TEMP=m8res
MERGE_DEVICE_LAYER {
	LAYERLIST = { m8 __PD_rm8_m8 }
}TEMP=m8
MERGE_DEVICE_LAYER {
	LAYERLIST = { m9res __PD_rm9_m9res }
}TEMP=m9res
MERGE_DEVICE_LAYER {
	LAYERLIST = { m9 __PD_rm9_m9 }
}TEMP=m9
MERGE_DEVICE_LAYER {
	LAYERLIST = { ndiffdio __PD_ND_ndiffdio }
}TEMP=ndiffdio
MERGE_DEVICE_LAYER {
	LAYERLIST = { pdiffdio __PD_PD_pdiffdio }
}TEMP=pdiffdio
CONNECT {
	ptap pwell BY [ OVERLAP TOUCH ] pwell_cont
	ntap nwnr BY [ OVERLAP TOUCH ] nwell_cont
	m1 nsd BY [ OVERLAP TOUCH ] codiff
	m1 psd BY [ OVERLAP TOUCH ] codiff
	m1 ntap BY [ OVERLAP TOUCH ] codiff
	m1 ptap BY [ OVERLAP TOUCH ] codiff
	ngate_12 BY [ OVERLAP TOUCH ] ponr
	pgate_12 BY [ OVERLAP TOUCH ] ponr
	ngate_25 BY [ OVERLAP TOUCH ] ponr
	pgate_25 BY [ OVERLAP TOUCH ] ponr
	ngate_12_lvt BY [ OVERLAP TOUCH ] ponr
	pgate_12_lvt BY [ OVERLAP TOUCH ] ponr
	ngate_12_hvt BY [ OVERLAP TOUCH ] ponr
	pgate_12_hvt BY [ OVERLAP TOUCH ] ponr
	m1 ponr BY [ OVERLAP TOUCH ] copoly
	m2 m1 BY [ OVERLAP TOUCH ] via1
	m3 m2 BY [ OVERLAP TOUCH ] via2
	m4 m3 BY [ OVERLAP TOUCH ] via3
	m5 m4 BY [ OVERLAP TOUCH ] via4
	m6 m5 BY [ OVERLAP TOUCH ] via5
	m7 m6 BY [ OVERLAP TOUCH ] via6
	m8 m7 BY [ OVERLAP TOUCH ] via7
	m9 m8 BY [ OVERLAP TOUCH ] via8
} CONNECT_DB = __CONNECT_DB_BCRczb__0001
TEXT_POLYGON M1PIN.TEXT {
	SIZE=0.01
	CELL_LIST = { * }
	TEXT_LIST = { * }
}TEMP=m1pin_marker
TEXT_POLYGON M2PIN.TEXT {
	SIZE=0.01
	CELL_LIST = { * }
	TEXT_LIST = { * }
}TEMP=m2pin_marker
TEXT_POLYGON M3PIN.TEXT {
	SIZE=0.01
	CELL_LIST = { * }
	TEXT_LIST = { * }
}TEMP=m3pin_marker
TEXT_POLYGON M4PIN.TEXT {
	SIZE=0.01
	CELL_LIST = { * }
	TEXT_LIST = { * }
}TEMP=m4pin_marker
TEXT_POLYGON M5PIN.TEXT {
	SIZE=0.01
	CELL_LIST = { * }
	TEXT_LIST = { * }
}TEMP=m5pin_marker
TEXT_POLYGON M6PIN.TEXT {
	SIZE=0.01
	CELL_LIST = { * }
	TEXT_LIST = { * }
}TEMP=m6pin_marker
TEXT_POLYGON M7PIN.TEXT {
	SIZE=0.01
	CELL_LIST = { * }
	TEXT_LIST = { * }
}TEMP=m7pin_marker
TEXT_POLYGON M8PIN.TEXT {
	SIZE=0.01
	CELL_LIST = { * }
	TEXT_LIST = { * }
}TEMP=m8pin_marker
TEXT_POLYGON M9PIN.TEXT {
	SIZE=0.01
	CELL_LIST = { * }
	TEXT_LIST = { * }
}TEMP=m9pin_marker
CONNECT {
	m1pin_marker BY [ OVERLAP TOUCH ] m1
	m2pin_marker BY [ OVERLAP TOUCH ] m2
	m3pin_marker BY [ OVERLAP TOUCH ] m3
	m4pin_marker BY [ OVERLAP TOUCH ] m4
	m5pin_marker BY [ OVERLAP TOUCH ] m5
	m6pin_marker BY [ OVERLAP TOUCH ] m6
	m7pin_marker BY [ OVERLAP TOUCH ] m7
	m8pin_marker BY [ OVERLAP TOUCH ] m8
	m9pin_marker BY [ OVERLAP TOUCH ] m9
} CONNECT_DB = __CONNECT_DB_BCRczb__0002
REMOVE_CONNECT_DB __CONNECT_DB_BCRczb__0001
TEXT { 
	m1pin_marker BY M1PIN.TEXT
	m2pin_marker BY M2PIN.TEXT
	m3pin_marker BY M3PIN.TEXT
	m4pin_marker BY M4PIN.TEXT
	m5pin_marker BY M5PIN.TEXT
	m6pin_marker BY M6PIN.TEXT
	m7pin_marker BY M7PIN.TEXT
	m8pin_marker BY M8PIN.TEXT
	m9pin_marker BY M9PIN.TEXT
}
CREATE_PORTS {
	TOP_CELL_ONLY=TRUE
	m1pin_marker BY m1pin_marker
	m2pin_marker BY m2pin_marker
	m3pin_marker BY m3pin_marker
	m4pin_marker BY m4pin_marker
	m5pin_marker BY m5pin_marker
	m6pin_marker BY m6pin_marker
	m7pin_marker BY m7pin_marker
	m8pin_marker BY m8pin_marker
	m9pin_marker BY m9pin_marker
	}
PROCESS_TEXT_OPENS {}
NMOS n12 ngate_12 nsd nsd pwell { 
	BODY_SELECT_LAYER = { __PD_n12_ngate_12 }
	MOS_HIERARCHICAL=FALSE;
	MOS_MULTITERM_EXTRACT=TRUE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_GAREA / EV_WIDTH;
} TEMP=generated_output_layer
PMOS p12 pgate_12 psd psd nwnr { 
	BODY_SELECT_LAYER = { __PD_p12_pgate_12 }
	MOS_HIERARCHICAL=FALSE;
	MOS_MULTITERM_EXTRACT=TRUE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_GAREA / EV_WIDTH;
} TEMP=generated_output_layer
NMOS n25 ngate_25 nsd nsd pwell { 
	BODY_SELECT_LAYER = { __PD_n25_ngate_25 }
	MOS_HIERARCHICAL=FALSE;
	MOS_MULTITERM_EXTRACT=TRUE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_GAREA / EV_WIDTH;
} TEMP=generated_output_layer
PMOS p25 pgate_25 psd psd nwnr { 
	BODY_SELECT_LAYER = { __PD_p25_pgate_25 }
	MOS_HIERARCHICAL=FALSE;
	MOS_MULTITERM_EXTRACT=TRUE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_GAREA / EV_WIDTH;
} TEMP=generated_output_layer
NMOS n12_lvt ngate_12_lvt nsd nsd pwell { 
	BODY_SELECT_LAYER = { __PD_n12_lvt_ngate_12_lvt }
	MOS_HIERARCHICAL=FALSE;
	MOS_MULTITERM_EXTRACT=TRUE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_GAREA / EV_WIDTH;
} TEMP=generated_output_layer
PMOS p12_lvt pgate_12_lvt psd psd nwnr { 
	BODY_SELECT_LAYER = { __PD_p12_lvt_pgate_12_lvt }
	MOS_HIERARCHICAL=FALSE;
	MOS_MULTITERM_EXTRACT=TRUE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_GAREA / EV_WIDTH;
} TEMP=generated_output_layer
NMOS n12_hvt ngate_12_hvt nsd nsd pwell { 
	BODY_SELECT_LAYER = { __PD_n12_hvt_ngate_12_hvt }
	MOS_HIERARCHICAL=FALSE;
	MOS_MULTITERM_EXTRACT=TRUE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_GAREA / EV_WIDTH;
} TEMP=generated_output_layer
PMOS p12_hvt pgate_12_hvt psd psd nwnr { 
	BODY_SELECT_LAYER = { __PD_p12_hvt_pgate_12_hvt }
	MOS_HIERARCHICAL=FALSE;
	MOS_MULTITERM_EXTRACT=TRUE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_GAREA / EV_WIDTH;
} TEMP=generated_output_layer
RES rppoly ppores ponr ponr { 
	BODY_SELECT_LAYER = { __PD_rppoly_ppores }
	RES_HIERARCHICAL=FALSE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_AREA / EV_WIDTH;  
	EV_RESVAL = 0;
} TEMP=generated_output_layer
RES rnpoly npores ponr ponr { 
	BODY_SELECT_LAYER = { __PD_rnpoly_npores }
	RES_HIERARCHICAL=FALSE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_AREA / EV_WIDTH;  
	EV_RESVAL = 0;
} TEMP=generated_output_layer
RES rppoly_wos ppores_sblk ponr ponr { 
	BODY_SELECT_LAYER = { __PD_rppoly_wos_ppores_sblk }
	RES_HIERARCHICAL=FALSE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_AREA / EV_WIDTH;  
	EV_RESVAL = 0;
} TEMP=generated_output_layer
RES rnpoly_wos npores_sblk ponr ponr { 
	BODY_SELECT_LAYER = { __PD_rnpoly_wos_npores_sblk }
	RES_HIERARCHICAL=FALSE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_AREA / EV_WIDTH;  
	EV_RESVAL = 0;
} TEMP=generated_output_layer
RES rm1 m1res m1 m1 { 
	BODY_SELECT_LAYER = { __PD_rm1_m1res }
	RES_HIERARCHICAL=FALSE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_AREA / EV_WIDTH;  
	RSH = 0.09;  
	EV_RESVAL = (RSH * EV_LENGTH) / EV_WIDTH;
} TEMP=generated_output_layer
RES rm2 m2res m2 m2 { 
	BODY_SELECT_LAYER = { __PD_rm2_m2res }
	RES_HIERARCHICAL=FALSE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_AREA / EV_WIDTH;  
	RSH = 0.09;  
	EV_RESVAL = (RSH * EV_LENGTH) / EV_WIDTH;
} TEMP=generated_output_layer
RES rm3 m3res m3 m3 { 
	BODY_SELECT_LAYER = { __PD_rm3_m3res }
	RES_HIERARCHICAL=FALSE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_AREA / EV_WIDTH;  
	RSH = 0.09;  
	EV_RESVAL = (RSH * EV_LENGTH) / EV_WIDTH;
} TEMP=generated_output_layer
RES rm4 m4res m4 m4 { 
	BODY_SELECT_LAYER = { __PD_rm4_m4res }
	RES_HIERARCHICAL=FALSE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_AREA / EV_WIDTH;  
	RSH = 0.09;  
	EV_RESVAL = (RSH * EV_LENGTH) / EV_WIDTH;
} TEMP=generated_output_layer
RES rm5 m5res m5 m5 { 
	BODY_SELECT_LAYER = { __PD_rm5_m5res }
	RES_HIERARCHICAL=FALSE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_AREA / EV_WIDTH;  
	RSH = 0.09;  
	EV_RESVAL = (RSH * EV_LENGTH) / EV_WIDTH;
} TEMP=generated_output_layer
RES rm6 m6res m6 m6 { 
	BODY_SELECT_LAYER = { __PD_rm6_m6res }
	RES_HIERARCHICAL=FALSE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_AREA / EV_WIDTH;  
	RSH = 0.09;  
	EV_RESVAL = (RSH * EV_LENGTH) / EV_WIDTH;
} TEMP=generated_output_layer
RES rm7 m7res m7 m7 { 
	BODY_SELECT_LAYER = { __PD_rm7_m7res }
	RES_HIERARCHICAL=FALSE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_AREA / EV_WIDTH;  
	RSH = 0.09;  
	EV_RESVAL = (RSH * EV_LENGTH) / EV_WIDTH;
} TEMP=generated_output_layer
RES rm8 m8res m8 m8 { 
	BODY_SELECT_LAYER = { __PD_rm8_m8res }
	RES_HIERARCHICAL=FALSE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_AREA / EV_WIDTH;  
	RSH = 0.09;  
	EV_RESVAL = (RSH * EV_LENGTH) / EV_WIDTH;
} TEMP=generated_output_layer
RES rm9 m9res m9 m9 { 
	BODY_SELECT_LAYER = { __PD_rm9_m9res }
	RES_HIERARCHICAL=FALSE;
	EV_WIDTH = (EV_W1 + EV_W2) / 2;  
	EV_LENGTH = EV_AREA / EV_WIDTH;  
	RSH = 0.028;  
	EV_RESVAL = (RSH * EV_LENGTH) / EV_WIDTH;
} TEMP=generated_output_layer
DIODE ND ndiffdio nsd pwell { 
	BODY_SELECT_LAYER = { __PD_ND_ndiffdio }
	DIODE_TYPE=NP;
	DIODE_HIERARCHICAL=FALSE;} TEMP=generated_output_layer
DIODE PD pdiffdio psd nwnr { 
	BODY_SELECT_LAYER = { __PD_PD_pdiffdio }
	DIODE_TYPE=PN;
	DIODE_HIERARCHICAL=FALSE;} TEMP=generated_output_layer
CONNECT_DEVICES
EQUATE NMOS n12=n12 GATE SRC DRN BULK { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_PARALLEL_CHAINS=TRUE 
	MERGE_SERIES=TRUE 
	MERGE_PATHS=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { NMOS-1 }
	REL_TOLERANCE[Length]= { +0, -0 }
	REL_TOLERANCE[Width]= { +0, -0 } }
EQUATE PMOS p12=p12 GATE SRC DRN BULK { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_PARALLEL_CHAINS=TRUE 
	MERGE_SERIES=TRUE 
	MERGE_PATHS=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { PMOS-1 }
	REL_TOLERANCE[Length]= { +0, -0 }
	REL_TOLERANCE[Width]= { +0, -0 } }
EQUATE NMOS n25=n25 GATE SRC DRN BULK { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_PARALLEL_CHAINS=TRUE 
	MERGE_SERIES=TRUE 
	MERGE_PATHS=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { NMOS-1 }
	REL_TOLERANCE[Length]= { +0, -0 }
	REL_TOLERANCE[Width]= { +0, -0 } }
EQUATE PMOS p25=p25 GATE SRC DRN BULK { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_PARALLEL_CHAINS=TRUE 
	MERGE_SERIES=TRUE 
	MERGE_PATHS=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { PMOS-1 }
	REL_TOLERANCE[Length]= { +0, -0 }
	REL_TOLERANCE[Width]= { +0, -0 } }
EQUATE NMOS n12_lvt=n12_lvt GATE SRC DRN BULK { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_PARALLEL_CHAINS=TRUE 
	MERGE_SERIES=TRUE 
	MERGE_PATHS=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { NMOS-1 }
	REL_TOLERANCE[Length]= { +0, -0 }
	REL_TOLERANCE[Width]= { +0, -0 } }
EQUATE PMOS p12_lvt=p12_lvt GATE SRC DRN BULK { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_PARALLEL_CHAINS=TRUE 
	MERGE_SERIES=TRUE 
	MERGE_PATHS=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { PMOS-1 }
	REL_TOLERANCE[Length]= { +0, -0 }
	REL_TOLERANCE[Width]= { +0, -0 } }
EQUATE NMOS n12_hvt=n12_hvt GATE SRC DRN BULK { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_PARALLEL_CHAINS=TRUE 
	MERGE_SERIES=TRUE 
	MERGE_PATHS=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { NMOS-1 }
	REL_TOLERANCE[Length]= { +0, -0 }
	REL_TOLERANCE[Width]= { +0, -0 } }
EQUATE PMOS p12_hvt=p12_hvt GATE SRC DRN BULK { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_PARALLEL_CHAINS=TRUE 
	MERGE_SERIES=TRUE 
	MERGE_PATHS=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { PMOS-1 }
	REL_TOLERANCE[Length]= { +0, -0 }
	REL_TOLERANCE[Width]= { +0, -0 } }
EQUATE RES rppoly=rppoly A B { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_SERIES=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { RES-1 }
	REL_TOLERANCE[Width]= { +0, -0 }
	REL_TOLERANCE[Length]= { +0, -0 } }
EQUATE RES rnpoly=rnpoly A B { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_SERIES=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { RES-1 }
	REL_TOLERANCE[Width]= { +0, -0 }
	REL_TOLERANCE[Length]= { +0, -0 } }
EQUATE RES rppoly_wos=rppoly_wos A B { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_SERIES=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { RES-1 }
	REL_TOLERANCE[Width]= { +0, -0 }
	REL_TOLERANCE[Length]= { +0, -0 } }
EQUATE RES rnpoly_wos=rnpoly_wos A B { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_SERIES=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { RES-1 }
	REL_TOLERANCE[Width]= { +0, -0 }
	REL_TOLERANCE[Length]= { +0, -0 } }
EQUATE RES rm1=rm1 A B { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_SERIES=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { RES-1 }
	REL_TOLERANCE[Width]= { +0, -0 }
	REL_TOLERANCE[Length]= { +0, -0 } }
EQUATE RES rm2=rm2 A B { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_SERIES=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { RES-1 }
	REL_TOLERANCE[Width]= { +0, -0 }
	REL_TOLERANCE[Length]= { +0, -0 } }
EQUATE RES rm3=rm3 A B { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_SERIES=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { RES-1 }
	REL_TOLERANCE[Width]= { +0, -0 }
	REL_TOLERANCE[Length]= { +0, -0 } }
EQUATE RES rm4=rm4 A B { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_SERIES=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { RES-1 }
	REL_TOLERANCE[Width]= { +0, -0 }
	REL_TOLERANCE[Length]= { +0, -0 } }
EQUATE RES rm5=rm5 A B { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_SERIES=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { RES-1 }
	REL_TOLERANCE[Width]= { +0, -0 }
	REL_TOLERANCE[Length]= { +0, -0 } }
EQUATE RES rm6=rm6 A B { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_SERIES=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { RES-1 }
	REL_TOLERANCE[Width]= { +0, -0 }
	REL_TOLERANCE[Length]= { +0, -0 } }
EQUATE RES rm7=rm7 A B { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_SERIES=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { RES-1 }
	REL_TOLERANCE[Width]= { +0, -0 }
	REL_TOLERANCE[Length]= { +0, -0 } }
EQUATE RES rm8=rm8 A B { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_SERIES=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { RES-1 }
	REL_TOLERANCE[Width]= { +0, -0 }
	REL_TOLERANCE[Length]= { +0, -0 } }
EQUATE RES rm9=rm9 A B { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	MERGE_SERIES=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Width Length }
	FILTER_OPTIONS = { RES-1 }
	REL_TOLERANCE[Width]= { +0, -0 }
	REL_TOLERANCE[Length]= { +0, -0 } }
EQUATE DIODE ND=ND CATHODE ANODE { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Area Pj }
	FILTER_OPTIONS = { NP-1 }
	REL_TOLERANCE[Area]= { +0, -0 }
	REL_TOLERANCE[Pj]= { +0, -0 } }
EQUATE DIODE PD=PD ANODE CATHODE { 
	FILTER=TRUE 
	MERGE_PARALLEL=TRUE 
	USE_TOTAL_WIDTH=TRUE 
	CHECK_PROPERTIES = {Area Pj }
	FILTER_OPTIONS = { PN-1 }
	REL_TOLERANCE[Area]= { +0, -0 }
	REL_TOLERANCE[Pj]= { +0, -0 } }
NETLIST {
	NETLIST_EMPTY_CELLS=FALSE
	NETLIST_DATABASE = /remote/SCRATCH_fs01/ANI_AL/Ani/fullflow/hercules/lvs/results/TOPCELLNAME.run_details/group
}
SPICE {
	MODEL_NAME_FORMAT=COMMENT 
	FORMAT=LVS 
	NETLIST_EMPTY_CELLS=FALSE
	VERBOSE=FALSE
	RES_CDL_FORMAT=FALSE
	CAP_CDL_FORMAT=FALSE
	LIMIT_SPICE_STRING=FALSE
	XREF_NETLIST_FILTERED_DEVICES=TRUE
	XREF=TRUE
	XREF_DEVICE_PREFIX = ld
	XREF_NETNAME_PREFIX = ln
	XREF_INSTNAME_PREFIX = li
	XREF_CELL_DELIMITER = _
	OUTPUT_FILE = TOPCELLNAME_lvs.sp
}
PROCESS_TEXT_OPENS {}
WRITE_EXTRACT_VIEW {
	LIBRARY_NAME = TOPCELLNAME_MILKYWAY
	LIBRARY_PATH = .
	GROUP_FILES = {
		ptap,
		via1,
		m6res,
		pgate_12_hvt,
		via2,
		m1res,
		m1,
		via3,
		m2,
		via4,
		pgate_12_lvt,
		m8res,
		npores,
		m9pin_marker,
		ngate_12_hvt,
		via5,
		pgate_25,
		m3,
		ndiffdio,
		m3res,
		m7pin_marker,
		via6,
		m4,
		m5pin_marker,
		ngate_12_lvt,
		via7,
		m5,
		m3pin_marker,
		via8,
		m6,
		codiff,
		nsd,
		m5res,
		m1pin_marker,
		psd,
		m7,
		m8,
		pwell,
		pwell_cont,
		pdiffdio,
		m9,
		ngate_12,
		m7res,
		ppores_sblk,
		m2res,
		npores_sblk,
		m8pin_marker,
		ponr,
		m9res,
		ppores,
		m6pin_marker,
		nwnr,
		copoly,
		ntap,
		m4res,
		m4pin_marker,
		nwell_cont,
		pgate_12,
		m2pin_marker,
		ngate_25
	}
}
PROCESS_TEXT_OPENS {}
DISCONNECT
CONNECT {
	ptap pwell BY [ OVERLAP TOUCH ] pwell_cont
	ntap nwnr BY [ OVERLAP TOUCH ] nwell_cont
	m1 nsd BY [ OVERLAP TOUCH ] codiff
	m1 psd BY [ OVERLAP TOUCH ] codiff
	m1 ntap BY [ OVERLAP TOUCH ] codiff
	m1 ptap BY [ OVERLAP TOUCH ] codiff
	ngate_12 BY [ OVERLAP TOUCH ] ponr
	pgate_12 BY [ OVERLAP TOUCH ] ponr
	ngate_25 BY [ OVERLAP TOUCH ] ponr
	pgate_25 BY [ OVERLAP TOUCH ] ponr
	ngate_12_lvt BY [ OVERLAP TOUCH ] ponr
	pgate_12_lvt BY [ OVERLAP TOUCH ] ponr
	ngate_12_hvt BY [ OVERLAP TOUCH ] ponr
	pgate_12_hvt BY [ OVERLAP TOUCH ] ponr
	m1 ponr BY [ OVERLAP TOUCH ] copoly
	m2 m1 BY [ OVERLAP TOUCH ] via1
	m3 m2 BY [ OVERLAP TOUCH ] via2
	m4 m3 BY [ OVERLAP TOUCH ] via3
	m5 m4 BY [ OVERLAP TOUCH ] via4
	m6 m5 BY [ OVERLAP TOUCH ] via5
	m7 m6 BY [ OVERLAP TOUCH ] via6
	m8 m7 BY [ OVERLAP TOUCH ] via7
	m9 m8 BY [ OVERLAP TOUCH ] via8
} CONNECT_DB = __CONNECT_DB_BCRczb__0001
CONNECT {
	m1pin_marker BY [ OVERLAP TOUCH ] m1
	m2pin_marker BY [ OVERLAP TOUCH ] m2
	m3pin_marker BY [ OVERLAP TOUCH ] m3
	m4pin_marker BY [ OVERLAP TOUCH ] m4
	m5pin_marker BY [ OVERLAP TOUCH ] m5
	m6pin_marker BY [ OVERLAP TOUCH ] m6
	m7pin_marker BY [ OVERLAP TOUCH ] m7
	m8pin_marker BY [ OVERLAP TOUCH ] m8
	m9pin_marker BY [ OVERLAP TOUCH ] m9
} CONNECT_DB = __CONNECT_DB_BCRczb__0002
WRITE_EXTRACT_VIEW {
	LIBRARY_NAME = TOPCELLNAME_MILKYWAY
	LIBRARY_PATH = .
	GROUP_FILES = {
		ptap,
		via1,
		m6res,
		pgate_12_hvt,
		via2,
		m1res,
		m1,
		via3,
		m2,
		via4,
		pgate_12_lvt,
		m8res,
		npores,
		m9pin_marker,
		ngate_12_hvt,
		via5,
		pgate_25,
		m3,
		ndiffdio,
		m3res,
		m7pin_marker,
		via6,
		m4,
		m5pin_marker,
		ngate_12_lvt,
		via7,
		m5,
		m3pin_marker,
		via8,
		m6,
		codiff,
		nsd,
		m5res,
		m1pin_marker,
		psd,
		m7,
		m8,
		pwell,
		pwell_cont,
		pdiffdio,
		m9,
		ngate_12,
		m7res,
		ppores_sblk,
		m2res,
		npores_sblk,
		m8pin_marker,
		ponr,
		m9res,
		ppores,
		m6pin_marker,
		nwnr,
		copoly,
		ntap,
		m4res,
		m4pin_marker,
		nwell_cont,
		pgate_12,
		m2pin_marker,
		ngate_25
	}
}
